A conventional magnetic disk device has a construction as shown in Japanese Unexamined Patent Publication No. 345967/1992. FIG. 26 shows the construction in such conventional technology. Further, a record format of a conventional magnetic disk device is shown in FIGS. 28(a)-28(d). FIG. 28(a) shows an index pulse which is generated once per rotation of a disk, FIG. 28(b) shows sector pulses which are generated at respective sectors, FIG. 28(c) shows a record format, and FIG. 28(d) shows a diagram magnifying the record format of each sector.
In FIG. 26, a magnetic disk device 150 sends and receives data to and from a host computer 101 such as a personal computer or a workstation via an interface bus 102. The magnetic disk device 150 includes a disk 109 of a disk type record medium, an interface controller 103 for controlling of sending and receiving data to and from the host computer 101 via the interface bus 102, a CPU 140 for controlling the inside of the magnetic disk device, a HDC (hard disk controller) 104 for controlling the access of data to the disk, so ECC (error correction code) circuit 105 for adding an error correcting/detecting code, a ENDEC (encoder/decoder) 106 for converting a code having a code form of NRZ into a run length limited code that is adapted to record on the magnetic disk and vice versa, a R/W (read/write) AMP 107 that is an amplifier, a head 108 for reading or recording magnetic information, a data buffer 111 for recording data, and a read control unit 110 for controlling a reading operation.
In FIG. 26, in writing data on the disk 109, firstly, write data which has been inputted from the host computer 101 is stored in the data buffer 111 through the interface bus 102, the interface controller 103 and the HDC 104. Next, an error correcting/detecting code is added to the data stored in the data buffer 11 by the ECC circuit 105 in the HDC 104. The code having a code form of NRZ of the write data which has been inputted from the host computer 101, is converted into a run length limited code such as (1,7) code or (2,7) code that is adapted to be recorded on the magnetic disk at the ENDEC 106. A voltage of the ENDEC 106 is amplified by the R/W AMP 107, and the amplified data is written on the magnetic disk 109 through the head 108. The run length limited code (RLL: Run Length Limited) restricts a continuation of “0” (called “run”) which are present between “1” and “1” in a data series. The first numeral in the parenthesis of (1,7) code or (2,7) code indicates a minimum value of the length of the run and the second numeral indicates the maximum value thereof. For instance, in the (1,7) code data, a “0” is always placed succeeding to “1” but there is no continuations of “0” by 8 or more. In this way, the recordable bit density is enhanced in comparison with the density of the magnetization reversal of the disk. The run length limited code signifies a record encoding wherein a data series is produced by conversion that is adapted to a characteristic of a recording and reproducing system.
Further, in reading data from the disk, the magnetic information written on the disk 109 is converted into an electric signal by the head 108, the voltage thereof is amplified by the R/W AMP 107, the analog signal is converted into a digital signal by the read control unit 110, and the run length limited code is converted into the NRZ code by the ENDEC 106. Next, error detection is performed by the ECC circuit 105, the error is corrected when it occurs in the read data, and the corrected data is stored in the data buffer 111. The data stored in the data buffer 111 is transferred to the host computer 101 through the HDC 104, the interface controller 103 and the interface bus 102.
Recently, PRML (Partial Response Maximum Likelihood) has been used as a next generation signal processing technology, as described in Japanese Unexamined Patent Publication No. 190934/1987, “Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel”, IEEE Transaction on Communications, vol. Com-34, No. 5, May, 1986, pps. 454-461, “Signal Processing System PRML Supports a Large Scale Memory Device of Next Generation”, Nikkei Electronics, Jan. 17, 1994 (No. 599), pps. 71-97 and the like. The PRML system detects the most likely data series (bit series of the maximum likelihood) among all the occurrable signal series by using the PR (Partial Response) system which performs an effective transfer by allowing inter-code interference of data and by using a decoding method called Viterbi algorithm. There are a number of systems in the PR system depending on what kind of inter-code interference is provided. For instance, PR (1,0;−1) (=PR4) is a system of providing a characteristic of (1D) (1+D) to a recording and reproducing system. In using the PRML system; There are many cases wherein (0,4,4) GCR (Group Coded Recording), or 8-9 conversion code is employed as the run length limited code, as shown in Japanese Examined Patent Publication No. 6699/1991. The (0,4,4) GCR signifies that the run is not smaller than 0 and not larger than 4, and in which the last numeral 4 signifies that the maximum value of the run is 4 in view of every other bit of a data series after encoding. Further, the 8-9 conversion Code is one of codes called block code, which signifies that an 8 bits data is converted into a 9 bits data. The block code converts m bits of an original data series into data having a bits (m≦n). It maps combinations suitable for the recording and reproducing characteristic in the a bits data from all the combinations of the m bits data.
With the larger capacity and higher density of a magnetic disk, the S/N is deteriorated, as described in “Design Acknowledging Medium Defect in Small Scale HDD Starts. Importance of Error Correction Using ECC Enhances”. Nikkei Electronics, Aug. 5, 1991 (No. 533), pps. 141-146. As a remedy for the deterioration of the S/N, a method has been used wherein redundancy bits of the error correcting code are increased and a strong error correcting code is added. As such an error correcting code, for instance, an error correcting code called BCH Code (Bose-Chaudbun-Hocquenghem Code) or Read-Solomon Code has been commercialized. In such an error correcting code, the redundancy bits should be increased in accordance with an increase in the number of error bits to be corrected.
FIG. 27 shows a system in block diagram form wherein an error correcting code is added using the PRML. In FIG. 27, the ECC circuit 105 in the HDC 104 adds an error correcting/detecting code to the write data stored in the data buffer 111, and the ENDEC 106 converts the code having a code form of NRZ of write data which has been inputted from the host computer 101, into the run length limited code that is suitable for recording on the magnetic disk. Further, a convolution encoding called pre-coding is carried out in the signal processing circuit 110 to perform the PRML, by which a regularity is provided to the data. Thereafter, in the R/W AMP 107, the voltage of the pre-coded write data is amplified, by which the writing is performed on the magnetic disk 109 by the head 108. In the PR system, since the inter-code interference is included in the reproduced waveform, it is necessary to remove the inter-code interference to reproduce the original data. Therefore, normally the operation of previously providing an inter-code interference which is inverse to that provided in the recording and reproducing system, is called pre-coding. For instance, an encoding which performs the pre-coding of PR (1.0,−1) (=PR4) to data of the NRZ (Non Return to Zero) system is called interleaved NRZI.
Further, in FIG. 27, in reading data, an electric signal which has been read from the head 108, is amplified by the R/W AMP 107, an error is corrected by ML decoding using the regularity provided to the precoding in the signal processing circuit 110, and the signal is digitized and inputted to the ENDEC 106. The run length limited code is converted into the NRZ code data in the ENDEC 106, successively, an error detecting is performed in the ECC circuit 105, and the error is corrected in case wherein the error has occurred in the read data.
Reference is made to FIG. 29 for an explanation of a behavior of propagation of error occurrence in case wherein, for instance, the PRML of Class 4 is employed as the PRML, a 8-8 convening code is employed as a run length limited code. As shown in FIG. 29, in case wherein an error of 1 bit occurs in reading data that has been recorded on a disk medium, when the data is decoded by the signal processing circuit 110 and is inputted to the ENDEC 106, it becomes an error of 2 bits (on the 8-8 converting code shown in FIG. 29) due to the characteristic of PRML Further, when the 8-8 converting code is converted into the NRZ signal in the ENDEC 106, it is magnified into an error of 2 bytes (on the NRZ code shown in FIG. 29) since it is encoded in the block code. When the length of data is 512 bytes, redundant bits of 48 bits at a minimum is required to correct a continuous 2 bytes in case of the Read-Solomon code.
Further, in the conventional technology, as shown in FIG. 28(d), the error correcting code (ECC) is added only to the write date, and no consideration is given to a case wherein an error occurs in a BYTESYNC region of a synchronization signal, or an identification portion including an area for storing an identification number that is identification information of each sector, or the like. At present, the BYTE-SYNC is provided with about 1 byte. However, when an error resistance function is to be provided to the NRZ signal in adopting the PRML or the 8-8 converting code, a BYTE-SYNC region of 5 bytes or more is necessary by adding redundant bits, which very much deteriorates a format efficiency (a ratio of a data capacity as compared with all the memory capacity). Similarly, at present, a CRC (error check code) of 2 bytes is added to the identification portion. However, to provide an error correction capability, a ECC of 4 bytes or more is necessary by adding redundant bits, which very much deteriorates the format efficiency.
Generally, in performing the error correction, the number of the redundant bits of the ECC is necessary to be two times or more of the number of bits to be corrected. The larger the size of error to be corrected, the more it is necessary to increase the redundant bits, which deteriorates the format efficiency.
As stated above, in the conventional technology, writing is performed by converting a data series into the run length limited code after providing the error correcting code thereto in encoding. Conversely, a decoding is performed by the PRML at the signal processing circuit 110 in decoding, and the error correction is performed by the error correcting code after inversely convening the run length limited code. Then, in occurrence of an error, an error occurs which has a regularity specific to a signal processing system that is carried out in the signal processing circuit 110, and the number of bits having the error is increased. Further, in converting it into the NRZ signal in the ENDEC 106, the size of error is further magnified. When the size of error to be corrected is magnified, it is necessary to increase redundant bits.
Further, as mentioned above, in the conventional technology, no consideration has been given to the occurrence of an error in the BYTESYNC region, the identification portion or the like, and it is desirable to provide the error correction capability to these regions.